1 2 3 6 5 4 approximate scale 1:1 low-voltage full-bridge brushless dc motor driver with hall element commutation a1441 description the a1441 is a full-bridge motor driver designed to drive low-voltage bipolar brushless dc motors. commutation of the motor is achieved by use of a single hall element sensor to detect the position of an alternating-pole ring magnet. a high density merged bipolar-cmos semiconductor process allows the integration of the hall element on the same ic as the motor control circuitry, providing a single-chip solution for enhanced reliability. all necessary circuitry is incorporated within the device package, eliminating the need for any external support components. a micropower sleep mode can be enabled by an external signal, to reduce current consumption for battery management in portable electronic devices. in addition, the device offers an active function for motor braking. the a1441 is optimized for vibration motor applications such as cellular phones, pagers, electronic toothbrushes, and hand- held video game controllers. these devices also drive low power fan motors designed with cogging plates. 1441-ds, rev. 2 features and benefits ? single-chip solution for high reliability ? chopper stabilization technique for precise signal response over operating range ? 2.0 to 4.0 v operation ? sleep mode pin allowing external logic signal enable/ disable to reduce average power consumption ? restart feature ? small package size functional block diagram continued on the next page? package: 6 contact mlp/dfn/son (suffix el)
low-voltage full-bridge brushless dc motor driver with hall element commutation a1441 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 3 1 5 4 6 vdd sleep nc vout2 vout1 gnd control drive control sleep mode driver terminal list table name number function el package vdd 1 supply voltage s l e e p 2 toggle sleep/enabled modes nc 3 no connection gnd 4 ground vout1 5 first output vout2 6 second output the small package outlines and low profiles make this device ideally suited for use in applications where printed circuit board area and component headroom are at a premium. it is available in a lead (pb) free (leadframe plating 100% matte tin) 6-pin surface mount mlp (microleadframe: dfn) package, with exposed pad for enhanced thermal dissipation. pin-out diagram absolute maximum ratings characteristic symbol notes rating supply voltage v dd 5.0 v reverse battery voltage v rdd ?0.3 v output voltage v out ?0.3 v to v dd + 0.3 v control input voltage v in(high) ?0.3 v to v dd + 0.3 v load current i load positive i load flow is from vout1 to vout2 150 ma magnetic flux density b unlimited operating ambient temperature t a range e ?40oc to 85oc maximum junction t j (max) 165oc storage temperature t stg ?65oc to 170oc selection guide part number package packing 1 A1441EELLT-T mlp 2 2 mm; 0.50 mm nom. height 3000 pieces/ 7-in. reel a1441seklt-t 2 1 for additional packing options, contact allegro. 2 these variants are in production but have been determined to be not for new design. this classifi- cation indicates that sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. status change: may 1, 2006. description (continued)
low-voltage full-bridge brushless dc motor driver with hall element commutation a1441 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com device characteristics over the voltage and temperature operating range, unless otherwise specified characteristics symbol test conditions min. typ. max. units supply voltage v dd running 2.0 ? 4.0 v total output saturation voltage 1 v out(sat) i load = 100 ma, v dd = 3.6 v ? ? 500 mv i load = 70 ma, v dd = 2.2 v ? ? 400 mv sleep mode supply current i dd(sleep) ??10 a load current rise time 2 t r(iload) v dd = 3.6 v ? 10 ? s chopping settling time 3 t s(chop) ?30? s s l e e p input threshold v inlo ? ? 0.5 v v inhi v dd ?0.7 ? ? v s l e e p input current i in ??1 a crossover dead time 4 t dt vout switching ? 2 ? s restart delay 5 t rs ? ? 225 ms magnetic switchpoints b op ?3575g b rp ?75 ?35 ? g b hys b op ? b rp ; b op > b rp ?70? g startup polarity v out1 bbop high ? v out2 bbop low ? 1 either v out(sat) = v q1(sat) + v q4(sat) or v out(sat) = v q2(sat) + v q3(sat) . total output saturation voltage is a sum of the voltages across the active output transistors. 2 time period required for current to change from 10% to 90% of it?s value. 3 chopping settling time is the required time to have valid device output after power up of the device. 4 crossover dead time is a time period during which all output transistors are switched off. 5 restart delay is a time period during which only one pair of the output transistors is switched on.
low-voltage full-bridge brushless dc motor driver with hall element commutation a1441 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com the products described herein are manufactured under one or more of the following u.s. patents: 5,045,920; 5,264,783; 5,44 2,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca t ions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright ? 2005, 2006, allegro microsystems, inc. 0.32 nom .013 1 6 0.35 0.15 .014 .006 0.55 0.45 .022 .018 0.05 0.00 .002 .000 0.15 ref .006 r0.20 ref .008 1.45 nom .057 1.45 nom .057 1.00 nom .039 1.00 nom .039 0.50 nom .020 0.50 nom .020 4x0.15 min .006 2x0.15 min .006 0.05 0 .002 .000 2.15 1.85 .085 .073 2.15 1.85 .085 .073 a b c seating plane c 0.08 [.003] 6x 0.50 .020 b 0.32 0.20 .013 .008 6x 0.10 [.004] m c a 0.05 [.002] m c 2 6 1 2 1 a c a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) hall element (not to scale) preliminary dimensions, for reference only (jedec ultra-thin mo-229uccd, except contact layout) dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown c d active area depth 0.233 [0.0092] u.s. customary dimensions controlling e reference land pattern layout; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) d 6 b 1.00 .0394 d e 1.00 .0394 d package el, 6 pin mlp/dfn/son
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